Modern integrated circuits are formed on the surfaces of semiconductor substrates, which are mostly silicon substrates. Semiconductor devices are isolated from each other by isolation structures formed close to the surface of the respective semiconductor substrates. The isolation structures include field oxides and shallow trench isolation (STI) regions.
Field oxides are often formed using local oxidation of silicon (LOCOS). A typical formation process includes blanket forming a mask layer on a silicon substrate, and then patterning the mask layer to expose certain areas of the underlying silicon substrate. A thermal oxidation is then performed in an oxygen-containing environment to oxidize the exposed portions of the silicon substrate. The mask layer is then removed.
With the down-scaling of integrated circuits, STI regions are increasingly used as the isolation structures. FIG. 1 illustrates a top view of an integrated circuit structure, which includes metal-oxide-semiconductor (MOS) devices 2 and 12. MOS device 2 includes gate poly 4 formed over active region 6. MOS device 12 includes gate poly 14 formed over active region 16. Active regions 6 and 16 are separated from each other and from other devices by STI regions 8, which include STI strips 81 parallel to the gate length direction (source-to-drain direction) of MOS devices 2 and 12, and STI strips 82 parallel to the gate width direction.
The formation of STI regions 8 is typically performed before the formation of MOS devices. During the subsequent high-temperature process steps, which may be performed at temperatures as high as about 700° C., stresses are generated due to the different coefficients of thermal expansion between STI regions 8 and active regions 6 and 16. STI regions 8 thus apply stresses to active regions 6 and 16, affecting the performance of MOS devices 2 and 12. In addition, the formation of source/drain regions requires dopant implantations. In the portions of active regions 6 and 16 near STI regions 8, dopant concentrations may have fluctuations due to the diffusion of the dopants into STI regions 8.
To make the situation worse, typically, the width W1 of STI strips 81 is greater than width W2 of STI strips 82. Voids are thus more likely to be generated in STI regions 82. This causes the stresses generated by STI regions 82 in the gate length direction to be adversely changed. Accordingly, what is needed in the art is a method for solving the above-discussed problems.